//----------------------------------------------------------------------------------------------------------------------
// Title      : .h file for TEMAC register space
// Author     : Xilinx Inc.
// -----------------------------------------------------------------------------
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
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// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
// Description: This header file contains AXI4 lite register information.
//----------------------------------------------------------------------------------------------------------------------

//// ==================================================
//// Register and Bitfield defines
//// ==================================================

//// Register type terminologies
//// XLNX_RW: Read/Write
//// XLNX_WO: Write-Only
//// XLNX_RO: Read-Only
//// XLNX_LH: Latching High
//// XLNX_LL: Latching Low
//// XLNX_COR: Clear-on-Read

////
//// Registers space
////

#define RECEIVED_BYTES_COUNTER_WORD_0_REG_OFFSET 0x00000200
//Desc
#define RECEIVED_BYTES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RECEIVED_BYTES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RECEIVED_BYTES_COUNTER_WORD_0_REG_SHIFT 0


#define RECEIVED_BYTES_COUNTER_WORD_1_REG_OFFSET 0x00000204
//Desc
#define RECEIVED_BYTES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RECEIVED_BYTES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RECEIVED_BYTES_COUNTER_WORD_1_REG_SHIFT 0


#define TRANSMITTED_BYTES_COUNTER_WORD_0_REG_OFFSET 0x00000208
//Desc
#define TRANSMITTED_BYTES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TRANSMITTED_BYTES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TRANSMITTED_BYTES_COUNTER_WORD_0_REG_SHIFT 0


#define TRANSMITTED_BYTES_COUNTER_WORD_1_REG_OFFSET 0x0000020C
//Desc
#define TRANSMITTED_BYTES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TRANSMITTED_BYTES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TRANSMITTED_BYTES_COUNTER_WORD_1_REG_SHIFT 0


#define UNDERSIZE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000210
//Desc
#define UNDERSIZE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define UNDERSIZE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define UNDERSIZE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define UNDERSIZE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000214
//Desc
#define UNDERSIZE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define UNDERSIZE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define UNDERSIZE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define FRAGMENT_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000218
//Desc
#define FRAGMENT_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define FRAGMENT_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define FRAGMENT_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define FRAGMENT_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x0000021C
//Desc
#define FRAGMENT_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define FRAGMENT_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define FRAGMENT_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define RX_64BYTE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000220
//Desc
#define RX_64BYTE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_64BYTE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_64BYTE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define RX_64BYTE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000224
//Desc
#define RX_64BYTE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_64BYTE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_64BYTE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define RX_65_127_BYTE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000228
//Desc
#define RX_65_127_BYTE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_65_127_BYTE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_65_127_BYTE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define RX_65_127_BYTE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x0000022C
//Desc
#define RX_65_127_BYTE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_65_127_BYTE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_65_127_BYTE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define RX_128_255_BYTE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000230
//Desc
#define RX_128_255_BYTE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_128_255_BYTE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_128_255_BYTE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define RX_128_255_BYTE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000234
//Desc
#define RX_128_255_BYTE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_128_255_BYTE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_128_255_BYTE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define RX_256_511_BYTE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000238
//Desc
#define RX_256_511_BYTE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_256_511_BYTE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_256_511_BYTE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define RX_256_511_BYTE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x0000023C
//Desc
#define RX_256_511_BYTE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_256_511_BYTE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_256_511_BYTE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define RX_512_1023_BYTE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000240
//Desc
#define RX_512_1023_BYTE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_512_1023_BYTE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_512_1023_BYTE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define RX_512_1023_BYTE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000244
//Desc
#define RX_512_1023_BYTE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_512_1023_BYTE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_512_1023_BYTE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define RX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000248
//Desc
#define RX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define RX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x0000024C
//Desc
#define RX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define RX_OVERSIZE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000250
//Desc
#define RX_OVERSIZE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_OVERSIZE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_OVERSIZE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define RX_OVERSIZE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000254
//Desc
#define RX_OVERSIZE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_OVERSIZE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_OVERSIZE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0







#define TX_64BYTE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000258
//Desc
#define TX_64BYTE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_64BYTE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_64BYTE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define TX_64BYTE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x0000025C
//Desc
#define TX_64BYTE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_64BYTE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_64BYTE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define TX_65_127_BYTE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000260
//Desc
#define TX_65_127_BYTE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_65_127_BYTE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_65_127_BYTE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define TX_65_127_BYTE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000264
//Desc
#define TX_65_127_BYTE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_65_127_BYTE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_65_127_BYTE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define TX_128_255_BYTE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000268
//Desc
#define TX_128_255_BYTE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_128_255_BYTE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_128_255_BYTE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define TX_128_255_BYTE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x0000026C
//Desc
#define TX_128_255_BYTE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_128_255_BYTE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_128_255_BYTE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define TX_256_511_BYTE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000270
//Desc
#define TX_256_511_BYTE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_256_511_BYTE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_256_511_BYTE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define TX_256_511_BYTE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000274
//Desc
#define TX_256_511_BYTE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_256_511_BYTE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_256_511_BYTE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define TX_512_1023_BYTE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000278
//Desc
#define TX_512_1023_BYTE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_512_1023_BYTE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_512_1023_BYTE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define TX_512_1023_BYTE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x0000027C
//Desc
#define TX_512_1023_BYTE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_512_1023_BYTE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_512_1023_BYTE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define TX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000280
//Desc
#define TX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define TX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000284
//Desc
#define TX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_1024_MAX_BYTE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define TX_OVERSIZE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000288
//Desc
#define TX_OVERSIZE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_OVERSIZE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_OVERSIZE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0


#define TX_OVERSIZE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x0000028C
//Desc
#define TX_OVERSIZE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_OVERSIZE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_OVERSIZE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define RX_GOOD_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000290
//Desc
#define RX_GOOD_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_GOOD_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_GOOD_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define RX_GOOD_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000294
//Desc
#define RX_GOOD_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_GOOD_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_GOOD_FRAMES_COUNTER_WORD_1_REG_SHIFT 0


#define RX_FRAME_CHECK_SEQUENCE_ERROR_COUNTER_WORD_0_REG_OFFSET 0x00000298
//Desc
#define RX_FRAME_CHECK_SEQUENCE_ERROR_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_FRAME_CHECK_SEQUENCE_ERROR_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_FRAME_CHECK_SEQUENCE_ERROR_COUNTER_WORD_0_REG_SHIFT 0

#define RX_FRAME_CHECK_SEQUENCE_ERROR_COUNTER_WORD_1_REG_OFFSET 0x0000029C
//Desc
#define RX_FRAME_CHECK_SEQUENCE_ERROR_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_FRAME_CHECK_SEQUENCE_ERROR_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_FRAME_CHECK_SEQUENCE_ERROR_COUNTER_WORD_1_REG_SHIFT 0

#define RX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x000002A0
//Desc
#define RX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define RX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x000002A4
//Desc
#define RX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define RX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x000002A8
//Desc
#define RX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define RX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x000002AC
//Desc
#define RX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define RX_GOOD_CONTROL_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x000002B0
//Desc
#define RX_GOOD_CONTROL_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_GOOD_CONTROL_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_GOOD_CONTROL_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define RX_GOOD_CONTROL_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x000002B4
//Desc
#define RX_GOOD_CONTROL_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_GOOD_CONTROL_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_GOOD_CONTROL_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define RX_LT_OUT_OF_RANGE_ERRORS_COUNTER_WORD_0_REG_OFFSET 0x000002B8
//Desc
#define RX_LT_OUT_OF_RANGE_ERRORS_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_LT_OUT_OF_RANGE_ERRORS_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_LT_OUT_OF_RANGE_ERRORS_COUNTER_WORD_0_REG_SHIFT 0

#define RX_LT_OUT_OF_RANGE_ERRORS_COUNTER_WORD_1_REG_OFFSET 0x000002BC
//Desc
#define RX_LT_OUT_OF_RANGE_ERRORS_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_LT_OUT_OF_RANGE_ERRORS_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_LT_OUT_OF_RANGE_ERRORS_COUNTER_WORD_1_REG_SHIFT 0

#define RX_GOOD_VLAN_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x000002C0
//Desc
#define RX_GOOD_VLAN_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_GOOD_VLAN_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_GOOD_VLAN_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define RX_GOOD_VLAN_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x000002C4
//Desc
#define RX_GOOD_VLAN_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_GOOD_VLAN_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_GOOD_VLAN_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define RX_GOOD_PAUSE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x000002C8
//Desc
#define RX_GOOD_PAUSE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_GOOD_PAUSE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_GOOD_PAUSE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define RX_GOOD_PAUSE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x000002CC
//Desc
#define RX_GOOD_PAUSE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_GOOD_PAUSE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_GOOD_PAUSE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define RX_BAD_OPCODE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x000002D0
//Desc
#define RX_BAD_OPCODE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_BAD_OPCODE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_BAD_OPCODE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define RX_BAD_OPCODE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x000002D4
//Desc
#define RX_BAD_OPCODE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_BAD_OPCODE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_BAD_OPCODE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define TX_GOOD_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x000002D8
//Desc
#define TX_GOOD_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_GOOD_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_GOOD_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define TX_GOOD_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x000002DC
//Desc
#define TX_GOOD_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_GOOD_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_GOOD_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define TX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x000002E0
//Desc
#define TX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define TX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x000002E4
//Desc
#define TX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_GOOD_BROADCAST_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define TX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x000002E8
//Desc
#define TX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define TX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x000002EC
//Desc
#define TX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_GOOD_MULTICAST_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define TX_UNDERRUN_ERRORS_COUNTER_WORD_0_REG_OFFSET 0x000002F0
//Desc
#define TX_UNDERRUN_ERRORS_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_UNDERRUN_ERRORS_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_UNDERRUN_ERRORS_COUNTER_WORD_0_REG_SHIFT 0

#define TX_UNDERRUN_ERRORS_COUNTER_WORD_1_REG_OFFSET 0x000002F4
//Desc
#define TX_UNDERRUN_ERRORS_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_UNDERRUN_ERRORS_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_UNDERRUN_ERRORS_COUNTER_WORD_1_REG_SHIFT 0

#define TX_GOOD_CONTROL_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x000002F8
//Desc
#define TX_GOOD_CONTROL_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_GOOD_CONTROL_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_GOOD_CONTROL_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define TX_GOOD_CONTROL_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x000002FC
//Desc
#define TX_GOOD_CONTROL_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_GOOD_CONTROL_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_GOOD_CONTROL_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define TX_GOOD_VLAN_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000300
//Desc
#define TX_GOOD_VLAN_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_GOOD_VLAN_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_GOOD_VLAN_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define TX_GOOD_VLAN_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000304
//Desc
#define TX_GOOD_VLAN_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_GOOD_VLAN_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_GOOD_VLAN_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define TX_GOOD_PAUSE_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000308
//Desc
#define TX_GOOD_PAUSE_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_GOOD_PAUSE_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_GOOD_PAUSE_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define TX_GOOD_PAUSE_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x0000030C
//Desc
#define TX_GOOD_PAUSE_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_GOOD_PAUSE_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_GOOD_PAUSE_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define TX_SINGLE_COLL_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000310
//Desc
#define TX_SINGLE_COLL_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_SINGLE_COLL_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_SINGLE_COLL_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define TX_SINGLE_COLL_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000314
//Desc
#define TX_SINGLE_COLL_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_SINGLE_COLL_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_SINGLE_COLL_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define TX_MULTIPLE_COLL_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000318
//Desc
#define TX_MULTIPLE_COLL_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_MULTIPLE_COLL_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_MULTIPLE_COLL_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define TX_MULTIPLE_COLL_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x0000031C
//Desc
#define TX_MULTIPLE_COLL_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_MULTIPLE_COLL_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_MULTIPLE_COLL_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define TX_DEFERRED_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000320
//Desc
#define TX_DEFERRED_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_DEFERRED_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_DEFERRED_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define TX_DEFERRED_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000324
//Desc
#define TX_DEFERRED_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_DEFERRED_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_DEFERRED_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define TX_LATE_COLL_COUNTER_WORD_0_REG_OFFSET 0x00000328
//Desc
#define TX_LATE_COLL_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_LATE_COLL_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_LATE_COLL_COUNTER_WORD_0_REG_SHIFT 0

#define TX_LATE_COLL_COUNTER_WORD_1_REG_OFFSET 0x0000032C
//Desc
#define TX_LATE_COLL_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_LATE_COLL_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_LATE_COLL_COUNTER_WORD_1_REG_SHIFT 0

#define TX_EXCESS_COLL_COUNTER_WORD_0_REG_OFFSET 0x00000330
//Desc
#define TX_EXCESS_COLL_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_EXCESS_COLL_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_EXCESS_COLL_COUNTER_WORD_0_REG_SHIFT 0

#define TX_EXCESS_COLL_COUNTER_WORD_1_REG_OFFSET 0x00000334
//Desc
#define TX_EXCESS_COLL_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_EXCESS_COLL_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_EXCESS_COLL_COUNTER_WORD_1_REG_SHIFT 0

#define TX_EXCESS_DEF_COUNTER_WORD_0_REG_OFFSET 0x00000338
//Desc
#define TX_EXCESS_DEF_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_EXCESS_DEF_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_EXCESS_DEF_COUNTER_WORD_0_REG_SHIFT 0

#define TX_EXCESS_DEF_COUNTER_WORD_1_REG_OFFSET 0x0000033C
//Desc
#define TX_EXCESS_DEF_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_EXCESS_DEF_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_EXCESS_DEF_COUNTER_WORD_1_REG_SHIFT 0

#define RX_ALIGNMENT_ERR_COUNTER_WORD_0_REG_OFFSET 0x00000340
//Desc
#define RX_ALIGNMENT_ERR_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_ALIGNMENT_ERR_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_ALIGNMENT_ERR_COUNTER_WORD_0_REG_SHIFT 0

#define RX_ALIGNMENT_ERR_COUNTER_WORD_1_REG_OFFSET 0x00000344
//Desc
#define RX_ALIGNMENT_ERR_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_ALIGNMENT_ERR_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_ALIGNMENT_ERR_COUNTER_WORD_1_REG_SHIFT 0

#define TX_PFC_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000348
//Desc
#define TX_PFC_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define TX_PFC_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define TX_PFC_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define TX_PFC_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x0000034C
//Desc
#define TX_PFC_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define TX_PFC_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define TX_PFC_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define RX_PFC_FRAMES_COUNTER_WORD_0_REG_OFFSET 0x00000350
//Desc
#define RX_PFC_FRAMES_COUNTER_WORD_0_REG_MASK 0xFFFFFFFF
#define RX_PFC_FRAMES_COUNTER_WORD_0_REG_ACCESS XLNX_RO
#define RX_PFC_FRAMES_COUNTER_WORD_0_REG_SHIFT 0

#define RX_PFC_FRAMES_COUNTER_WORD_1_REG_OFFSET 0x00000354
//Desc
#define RX_PFC_FRAMES_COUNTER_WORD_1_REG_MASK 0xFFFFFFFF
#define RX_PFC_FRAMES_COUNTER_WORD_1_REG_ACCESS XLNX_RO
#define RX_PFC_FRAMES_COUNTER_WORD_1_REG_SHIFT 0

#define RX_CONF_WORD_0_REG_OFFSET 0x00000400
//Desc
#define RX_CONF_WORD_0_REG_PAUSE_FRM_MAC_SA_MASK 0xFFFFFFFF
#define RX_CONF_WORD_0_REG_PAUSE_FRM_MAC_SA_ACCESS XLNX_RW
#define RX_CONF_WORD_0_REG_PAUSE_FRM_MAC_SA_SHIFT 0 
#define RX_CONF_WORD_0_REG_PAUSE_FRM_MAC_SA_DEFAULT 0xFFFFFFFF 

#define RX_CONF_WORD_1_REG_OFFSET 0x00000404
//Desc
#define RX_CONF_WORD_1_REG_PAUSE_FRM_MAC_SA_MASK 0x0000FFFF
#define RX_CONF_WORD_1_REG_PAUSE_FRM_MAC_SA_ACCESS XLNX_RW
#define RX_CONF_WORD_1_REG_PAUSE_FRM_MAC_SA_SHIFT 0 
#define RX_CONF_WORD_1_REG_PAUSE_FRM_MAC_SA_DEFAULT 0xFFFF 
//Desc
#define RX_CONF_WORD_1_REG_CTL_FRM_LEN_CHK_DISABLE_MASK 0x01000000
#define RX_CONF_WORD_1_REG_CTL_FRM_LEN_CHK_DISABLE_ACCESS XLNX_RW
#define RX_CONF_WORD_1_REG_CTL_FRM_LEN_CHK_DISABLE_SHIFT 24
#define RX_CONF_WORD_1_REG_CTL_FRM_LEN_CHK_DISABLE_DEFAULT 0x0
//Desc
#define RX_CONF_WORD_1_REG_LT_ERR_CHK_DISABLE_MASK 0x02000000
#define RX_CONF_WORD_1_REG_LT_ERR_CHK_DISABLE_ACCESS XLNX_RW
#define RX_CONF_WORD_1_REG_LT_ERR_CHK_DISABLE_SHIFT 25
#define RX_CONF_WORD_1_REG_LT_ERR_CHK_DISABLE_DEFAULT 0x0
//Desc
#define RX_CONF_WORD_1_REG_HALF_DUPLEX_MASK 0x04000000
#define RX_CONF_WORD_1_REG_HALF_DUPLEX_ACCESS XLNX_RW
#define RX_CONF_WORD_1_REG_HALF_DUPLEX_SHIFT 26
#define RX_CONF_WORD_1_REG_HALF_DUPLEX_DEFAULT 0x0
//Desc
#define RX_CONF_WORD_1_REG_VLAN_ENABLE_MASK 0x08000000
#define RX_CONF_WORD_1_REG_VLAN_ENABLE_ACCESS XLNX_RW
#define RX_CONF_WORD_1_REG_VLAN_ENABLE_SHIFT 27
#define RX_CONF_WORD_1_REG_VLAN_ENABLE_DEFAULT 0x0
//Desc
#define RX_CONF_WORD_1_REG_RX_ENABLE_MASK 0x10000000
#define RX_CONF_WORD_1_REG_RX_ENABLE_ACCESS XLNX_RW
#define RX_CONF_WORD_1_REG_RX_ENABLE_SHIFT 28
#define RX_CONF_WORD_1_REG_RX_ENABLE_DEFAULT 0x1
//Desc
#define RX_CONF_WORD_1_REG_INBAND_FCS_ENBALE_MASK 0x20000000
#define RX_CONF_WORD_1_REG_INBAND_FCS_ENBALE_ACCESS XLNX_RW
#define RX_CONF_WORD_1_REG_INBAND_FCS_ENBALE_SHIFT 29
#define RX_CONF_WORD_1_REG_INBAND_FCS_ENBALE_DEFAULT 0x0
//Desc
#define RX_CONF_WORD_1_REG_JUMBO_FRAME_ENBALE_MASK 0x40000000
#define RX_CONF_WORD_1_REG_JUMBO_FRAME_ENBALE_ACCESS XLNX_RW
#define RX_CONF_WORD_1_REG_JUMBO_FRAME_ENBALE_SHIFT 30
#define RX_CONF_WORD_1_REG_JUMBO_FRAME_ENBALE_DEFAULT 0x0
//Desc
#define RX_CONF_WORD_1_REG_RESET_MASK 0x80000000
#define RX_CONF_WORD_1_REG_RESET_ACCESS XLNX_RW
#define RX_CONF_WORD_1_REG_RESET_SHIFT 31
#define RX_CONF_WORD_1_REG_RESET_DEFAULT 0x0

#define TX_CONF_WORD_0_REG_OFFSET 0x00000408
//Desc
#define TX_CONF_WORD_0_REG_IFG_ADJUST_ENABLE_MASK 0x02000000
#define TX_CONF_WORD_0_REG_IFG_ADJUST_ENABLE_ACCESS XLNX_RW
#define TX_CONF_WORD_0_REG_IFG_ADJUST_ENABLE_SHIFT 25
#define TX_CONF_WORD_0_REG_IFG_ADJUST_ENABLE_DEFAULT 0x0
//Desc
#define TX_CONF_WORD_0_REG_HALF_DUPLEX_MASK 0x04000000
#define TX_CONF_WORD_0_REG_HALF_DUPLEX_ACCESS XLNX_RW
#define TX_CONF_WORD_0_REG_HALF_DUPLEX_SHIFT 26
#define TX_CONF_WORD_0_REG_HALF_DUPLEX_DEFAULT 0x0
//Desc
#define TX_CONF_WORD_0_REG_VLAN_ENABLE_MASK 0x08000000
#define TX_CONF_WORD_0_REG_VLAN_ENABLE_ACCESS XLNX_RW
#define TX_CONF_WORD_0_REG_VLAN_ENABLE_SHIFT 27
#define TX_CONF_WORD_0_REG_VLAN_ENABLE_DEFAULT 0x0
//Desc
#define TX_CONF_WORD_0_REG_TX_ENABLE_MASK 0x10000000
#define TX_CONF_WORD_0_REG_TX_ENABLE_ACCESS XLNX_RW
#define TX_CONF_WORD_0_REG_TX_ENABLE_SHIFT 28
#define TX_CONF_WORD_0_REG_TX_ENABLE_DEFAULT 0x1
//Desc
#define TX_CONF_WORD_0_REG_INBAND_FCS_ENBALE_MASK 0x20000000
#define TX_CONF_WORD_0_REG_INBAND_FCS_ENBALE_ACCESS XLNX_RW
#define TX_CONF_WORD_0_REG_INBAND_FCS_ENBALE_SHIFT 29
#define TX_CONF_WORD_0_REG_INBAND_FCS_ENBALE_DEFAULT 0x0
//Desc
#define TX_CONF_WORD_0_REG_JUMBO_FRAME_ENBALE_MASK 0x40000000
#define TX_CONF_WORD_0_REG_JUMBO_FRAME_ENBALE_ACCESS XLNX_RW
#define TX_CONF_WORD_0_REG_JUMBO_FRAME_ENBALE_SHIFT 30
#define TX_CONF_WORD_0_REG_JUMBO_FRAME_ENBALE_DEFAULT 0x0
//Desc
#define TX_CONF_WORD_0_REG_RESET_MASK 0x80000000
#define TX_CONF_WORD_0_REG_RESET_ACCESS XLNX_RW
#define TX_CONF_WORD_0_REG_RESET_SHIFT 31
#define TX_CONF_WORD_0_REG_RESET_DEFAULT 0x0

#define FLOW_CONTROL_CONF_WORD_REG_OFFSET 0x0000040C
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_RX_P0_PAUSE_ENABLE_MASK 0x00000001
#define FLOW_CONTROL_CONF_WORD_REG_RX_P0_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_RX_P0_PAUSE_ENABLE_SHIFT 0
#define FLOW_CONTROL_CONF_WORD_REG_RX_P0_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_RX_P1_PAUSE_ENABLE_MASK 0x00000002
#define FLOW_CONTROL_CONF_WORD_REG_RX_P1_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_RX_P1_PAUSE_ENABLE_SHIFT 1
#define FLOW_CONTROL_CONF_WORD_REG_RX_P1_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_RX_P2_PAUSE_ENABLE_MASK 0x00000004
#define FLOW_CONTROL_CONF_WORD_REG_RX_P2_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_RX_P2_PAUSE_ENABLE_SHIFT 2
#define FLOW_CONTROL_CONF_WORD_REG_RX_P2_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_RX_P3_PAUSE_ENABLE_MASK 0x00000008
#define FLOW_CONTROL_CONF_WORD_REG_RX_P3_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_RX_P3_PAUSE_ENABLE_SHIFT 3
#define FLOW_CONTROL_CONF_WORD_REG_RX_P3_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_RX_P4_PAUSE_ENABLE_MASK 0x00000010
#define FLOW_CONTROL_CONF_WORD_REG_RX_P4_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_RX_P4_PAUSE_ENABLE_SHIFT 4
#define FLOW_CONTROL_CONF_WORD_REG_RX_P4_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_RX_P5_PAUSE_ENABLE_MASK 0x00000020
#define FLOW_CONTROL_CONF_WORD_REG_RX_P5_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_RX_P5_PAUSE_ENABLE_SHIFT 5
#define FLOW_CONTROL_CONF_WORD_REG_RX_P5_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_RX_P6_PAUSE_ENABLE_MASK 0x00000040
#define FLOW_CONTROL_CONF_WORD_REG_RX_P6_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_RX_P6_PAUSE_ENABLE_SHIFT 6
#define FLOW_CONTROL_CONF_WORD_REG_RX_P6_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_RX_P7_PAUSE_ENABLE_MASK 0x00000080
#define FLOW_CONTROL_CONF_WORD_REG_RX_P7_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_RX_P7_PAUSE_ENABLE_SHIFT 7
#define FLOW_CONTROL_CONF_WORD_REG_RX_P7_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_TX_P0_PAUSE_ENABLE_MASK 0x00000100
#define FLOW_CONTROL_CONF_WORD_REG_TX_P0_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_TX_P0_PAUSE_ENABLE_SHIFT 8
#define FLOW_CONTROL_CONF_WORD_REG_TX_P0_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_TX_P1_PAUSE_ENABLE_MASK 0x00000200
#define FLOW_CONTROL_CONF_WORD_REG_TX_P1_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_TX_P1_PAUSE_ENABLE_SHIFT 9
#define FLOW_CONTROL_CONF_WORD_REG_TX_P1_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_TX_P2_PAUSE_ENABLE_MASK 0x00000400
#define FLOW_CONTROL_CONF_WORD_REG_TX_P2_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_TX_P2_PAUSE_ENABLE_SHIFT 10
#define FLOW_CONTROL_CONF_WORD_REG_TX_P2_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_TX_P3_PAUSE_ENABLE_MASK 0x00000800
#define FLOW_CONTROL_CONF_WORD_REG_TX_P3_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_TX_P3_PAUSE_ENABLE_SHIFT 11
#define FLOW_CONTROL_CONF_WORD_REG_TX_P3_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_TX_P4_PAUSE_ENABLE_MASK 0x00001000
#define FLOW_CONTROL_CONF_WORD_REG_TX_P4_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_TX_P4_PAUSE_ENABLE_SHIFT 12
#define FLOW_CONTROL_CONF_WORD_REG_TX_P4_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_TX_P5_PAUSE_ENABLE_MASK 0x00002000
#define FLOW_CONTROL_CONF_WORD_REG_TX_P5_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_TX_P5_PAUSE_ENABLE_SHIFT 13
#define FLOW_CONTROL_CONF_WORD_REG_TX_P5_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_TX_P6_PAUSE_ENABLE_MASK 0x00004000
#define FLOW_CONTROL_CONF_WORD_REG_TX_P6_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_TX_P6_PAUSE_ENABLE_SHIFT 14
#define FLOW_CONTROL_CONF_WORD_REG_TX_P6_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_TX_P7_PAUSE_ENABLE_MASK 0x00008000
#define FLOW_CONTROL_CONF_WORD_REG_TX_P7_PAUSE_ENABLE_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_TX_P7_PAUSE_ENABLE_SHIFT 15
#define FLOW_CONTROL_CONF_WORD_REG_TX_P7_PAUSE_ENABLE_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_TX_AUTO_XON_MASK 0x00100000
#define FLOW_CONTROL_CONF_WORD_REG_TX_AUTO_XON_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_TX_AUTO_XON_SHIFT 20
#define FLOW_CONTROL_CONF_WORD_REG_TX_AUTO_XON_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_PFC_ENABLE_RX_MASK 0x02000000
#define FLOW_CONTROL_CONF_WORD_REG_PFC_ENABLE_RX_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_PFC_ENABLE_RX_SHIFT 25
#define FLOW_CONTROL_CONF_WORD_REG_PFC_ENABLE_RX_DEFAULT 0x0
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_PFC_ENABLE_TX_MASK 0x04000000
#define FLOW_CONTROL_CONF_WORD_REG_PFC_ENABLE_TX_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_PFC_ENABLE_TX_SHIFT 26
#define FLOW_CONTROL_CONF_WORD_REG_PFC_ENABLE_TX_DEFAULT 0x0
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_FLOW_CONTROL_ENABLE_RX_MASK 0x20000000
#define FLOW_CONTROL_CONF_WORD_REG_FLOW_CONTROL_ENABLE_RX_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_FLOW_CONTROL_ENABLE_RX_SHIFT 29
#define FLOW_CONTROL_CONF_WORD_REG_FLOW_CONTROL_ENABLE_RX_DEFAULT 0x1
//Desc
#define FLOW_CONTROL_CONF_WORD_REG_FLOW_CONTROL_ENABLE_TX_MASK 0x40000000
#define FLOW_CONTROL_CONF_WORD_REG_FLOW_CONTROL_ENABLE_TX_ACCESS XLNX_RW
#define FLOW_CONTROL_CONF_WORD_REG_FLOW_CONTROL_ENABLE_TX_SHIFT 30
#define FLOW_CONTROL_CONF_WORD_REG_FLOW_CONTROL_ENABLE_TX_DEFAULT 0x1

#define MAC_SPEED_CONF_WORD_REG_OFFSET 0x00000410
// Desc
#define MAC_SPEED_CONF_WORD_REG_MAC_SPEED_CONF_MASK 0xC0000000
#define MAC_SPEED_CONF_WORD_REG_MAC_SPEED_CONF_ACCESS XLNX_RW
#define MAC_SPEED_CONF_WORD_REG_MAC_SPEED_CONF_SHIFT 30
#define MAC_SPEED_CONF_WORD_REG_MAC_SPEED_CONF_DEFAULT 0x2

#define RX_MAC_FRAME_CONF_WORD_REG_OFFSET 0x00000414
// Desc
#define RX_MAC_FRAME_CONF_WORD_REG_RX_MAX_FRAME_LENGTH_MASK 0x00007FFF
#define RX_MAC_FRAME_CONF_WORD_REG_RX_MAX_FRAME_LENGTH_ACCESS XLNX_RW
#define RX_MAC_FRAME_CONF_WORD_REG_RX_MAX_FRAME_LENGTH_SHIFT 0
#define RX_MAC_FRAME_CONF_WORD_REG_RX_MAX_FRAME_LENGTH_DEFAULT 0x7D0
// Desc
#define RX_MAC_FRAME_CONF_WORD_REG_RX_MAX_FRAME_ENABLE_MASK 0x00010000
#define RX_MAC_FRAME_CONF_WORD_REG_RX_MAX_FRAME_ENABLE_ACCESS XLNX_RW
#define RX_MAC_FRAME_CONF_WORD_REG_RX_MAX_FRAME_ENABLE_SHIFT 16
#define RX_MAC_FRAME_CONF_WORD_REG_RX_MAX_FRAME_ENABLE_DEFAULT 0x0

#define TX_MAC_FRAME_CONF_WORD_REG_OFFSET 0x00000418
// Desc
#define TX_MAC_FRAME_CONF_WORD_REG_TX_MAX_FRAME_LENGTH_MASK 0x00007FFF
#define TX_MAC_FRAME_CONF_WORD_REG_TX_MAX_FRAME_LENGTH_ACCESS XLNX_RW
#define TX_MAC_FRAME_CONF_WORD_REG_TX_MAX_FRAME_LENGTH_SHIFT 0
#define TX_MAC_FRAME_CONF_WORD_REG_TX_MAX_FRAME_LENGTH_DEFAULT 0x7D0
// Desc
#define TX_MAC_FRAME_CONF_WORD_REG_TX_MAX_FRAME_ENABLE_MASK 0x00010000
#define TX_MAC_FRAME_CONF_WORD_REG_TX_MAX_FRAME_ENABLE_ACCESS XLNX_RW
#define TX_MAC_FRAME_CONF_WORD_REG_TX_MAX_FRAME_ENABLE_SHIFT 16
#define TX_MAC_FRAME_CONF_WORD_REG_TX_MAX_FRAME_ENABLE_DEFAULT 0x0

#define PRIORITY_0_QUANTA_REFRESH_REG_OFFSET 0x00000480
// Desc
#define PRIORITY_0_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_MASK 0x0000FFFF
#define PRIORITY_0_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_ACCESS XLNX_RW
#define PRIORITY_0_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_SHIFT 0
#define PRIORITY_0_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_DEFAULT 0xFFFF
// Desc
#define PRIORITY_0_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_MASK 0xFFFF0000
#define PRIORITY_0_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_ACCESS XLNX_RW
#define PRIORITY_0_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_SHIFT 16
#define PRIORITY_0_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_DEFAULT 0xFF00

#define PRIORITY_1_QUANTA_REFRESH_REG_OFFSET 0x00000484
// Desc
#define PRIORITY_1_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_MASK 0x0000FFFF
#define PRIORITY_1_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_ACCESS XLNX_RW
#define PRIORITY_1_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_SHIFT 0
#define PRIORITY_1_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_DEFAULT 0xFFFF
// Desc
#define PRIORITY_1_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_MASK 0xFFFF0000
#define PRIORITY_1_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_ACCESS XLNX_RW
#define PRIORITY_1_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_SHIFT 16
#define PRIORITY_1_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_DEFAULT 0xFF00

#define PRIORITY_2_QUANTA_REFRESH_REG_OFFSET 0x00000488
// Desc
#define PRIORITY_2_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_MASK 0x0000FFFF
#define PRIORITY_2_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_ACCESS XLNX_RW
#define PRIORITY_2_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_SHIFT 0
#define PRIORITY_2_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_DEFAULT 0xFFFF
// Desc
#define PRIORITY_2_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_MASK 0xFFFF0000
#define PRIORITY_2_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_ACCESS XLNX_RW
#define PRIORITY_2_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_SHIFT 16
#define PRIORITY_2_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_DEFAULT 0xFF00

#define PRIORITY_3_QUANTA_REFRESH_REG_OFFSET 0x0000048C
// Desc
#define PRIORITY_3_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_MASK 0x0000FFFF
#define PRIORITY_3_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_ACCESS XLNX_RW
#define PRIORITY_3_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_SHIFT 0
#define PRIORITY_3_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_DEFAULT 0xFFFF
// Desc
#define PRIORITY_3_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_MASK 0xFFFF0000
#define PRIORITY_3_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_ACCESS XLNX_RW
#define PRIORITY_3_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_SHIFT 16
#define PRIORITY_3_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_DEFAULT 0xFF00

#define PRIORITY_4_QUANTA_REFRESH_REG_OFFSET 0x00000490
// Desc
#define PRIORITY_4_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_MASK 0x0000FFFF
#define PRIORITY_4_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_ACCESS XLNX_RW
#define PRIORITY_4_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_SHIFT 0
#define PRIORITY_4_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_DEFAULT 0xFFFF
// Desc
#define PRIORITY_4_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_MASK 0xFFFF0000
#define PRIORITY_4_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_ACCESS XLNX_RW
#define PRIORITY_4_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_SHIFT 16
#define PRIORITY_4_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_DEFAULT 0xFF00

#define PRIORITY_5_QUANTA_REFRESH_REG_OFFSET 0x00000494
// Desc
#define PRIORITY_5_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_MASK 0x0000FFFF
#define PRIORITY_5_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_ACCESS XLNX_RW
#define PRIORITY_5_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_SHIFT 0
#define PRIORITY_5_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_DEFAULT 0xFFFF
// Desc
#define PRIORITY_5_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_MASK 0xFFFF0000
#define PRIORITY_5_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_ACCESS XLNX_RW
#define PRIORITY_5_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_SHIFT 16
#define PRIORITY_5_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_DEFAULT 0xFF00

#define PRIORITY_6_QUANTA_REFRESH_REG_OFFSET 0x00000498
// Desc
#define PRIORITY_6_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_MASK 0x0000FFFF
#define PRIORITY_6_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_ACCESS XLNX_RW
#define PRIORITY_6_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_SHIFT 0
#define PRIORITY_6_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_DEFAULT 0xFFFF
// Desc
#define PRIORITY_6_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_MASK 0xFFFF0000
#define PRIORITY_6_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_ACCESS XLNX_RW
#define PRIORITY_6_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_SHIFT 16
#define PRIORITY_6_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_DEFAULT 0xFF00

#define PRIORITY_7_QUANTA_REFRESH_REG_OFFSET 0x0000049C
// Desc
#define PRIORITY_7_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_MASK 0x0000FFFF
#define PRIORITY_7_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_ACCESS XLNX_RW
#define PRIORITY_7_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_SHIFT 0
#define PRIORITY_7_QUANTA_REFRESH_REG_PER_QUANTA_VALUE_DEFAULT 0xFFFF
// Desc
#define PRIORITY_7_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_MASK 0xFFFF0000
#define PRIORITY_7_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_ACCESS XLNX_RW
#define PRIORITY_7_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_SHIFT 16
#define PRIORITY_7_QUANTA_REFRESH_REG_PER_QUANTA_REFRESH_VALUE_DEFAULT 0xFF00

#define LEGACY_PAUSE_REFRESH_REG_OFFSET 0x000004A0
// Desc
#define LEGACY_PAUSE_REFRESH_REG_PAUSE_QUANTA_REFRESH_VALUE_MASK 0xFFFF0000
#define LEGACY_PAUSE_REFRESH_REG_PAUSE_QUANTA_REFRESH_VALUE_ACCESS XLNX_RW
#define LEGACY_PAUSE_REFRESH_REG_PAUSE_QUANTA_REFRESH_VALUE_SHIFT 16
#define LEGACY_PAUSE_REFRESH_REG_PAUSE_QUANTA_REFRESH_VALUE_DEFAULT 0xFF00

#define ID_REG_OFFSET 0x000004F8
//Desc
#define ID_REG_PATCH_LEVEL_MASK 0x000000FF
#define ID_REG_PATCH_LEVEL_ACCESS XLNX_RO
#define ID_REG_PATCH_LEVEL_SHIFT 0
#define ID_REG_PATCH_LEVEL_DEFAULT 0x00
//Desc
#define ID_REG_MINOR_REV_MASK 0x00FF0000
#define ID_REG_MINOR_REV_ACCESS XLNX_RO
#define ID_REG_MINOR_REV_SHIFT 16
#define ID_REG_MINOR_REV_DEFAULT 0x00
//Desc
#define ID_REG_MAJOR_REV_MASK 0xFF000000
#define ID_REG_MAJOR_REV_ACCESS XLNX_RO
#define ID_REG_MAJOR_REV_SHIFT 24
#define ID_REG_MAJOR_REV_DEFAULT 0x00

#define ABILITY_REG_OFFSET 0x000004FC
//Desc
#define ABILITY_REG_10M_ABILITY_MASK 0x00000001
#define ABILITY_REG_10M_ABILITY_ACCESS XLNX_RO
#define ABILITY_REG_10M_ABILITY_SHIFT 0
#define ABILITY_REG_10M_ABILITY_DEFAULT 0x0
//Desc
#define ABILITY_REG_100M_ABILITY_MASK 0x00000002
#define ABILITY_REG_100M_ABILITY_ACCESS XLNX_RO
#define ABILITY_REG_100M_ABILITY_SHIFT 1
#define ABILITY_REG_100M_ABILITY_DEFAULT 0x0
//Desc
#define ABILITY_REG_1G_ABILITY_MASK 0x00000004
#define ABILITY_REG_1G_ABILITY_ACCESS XLNX_RO
#define ABILITY_REG_1G_ABILITY_SHIFT 2
#define ABILITY_REG_1G_ABILITY_DEFAULT 0x0
//Desc
#define ABILITY_REG_2G5_ABILITY_MASK 0x00000008
#define ABILITY_REG_2G5_ABILITY_ACCESS XLNX_RO
#define ABILITY_REG_2G5_ABILITY_SHIFT 3
#define ABILITY_REG_2G5_ABILITY_DEFAULT 0x0
//Desc
#define ABILITY_REG_STATISTICS_COUNTERS_AVAILABLE_MASK 0x00000100
#define ABILITY_REG_STATISTICS_COUNTERS_AVAILABLE_ACCESS XLNX_RO
#define ABILITY_REG_STATISTICS_COUNTERS_AVAILABLE_SHIFT 8
#define ABILITY_REG_STATISTICS_COUNTERS_AVAILABLE_DEFAULT 0x0
//Desc
#define ABILITY_REG_HALF_DUPLEX_CAPABLE_MASK 0x00000200
#define ABILITY_REG_HALF_DUPLEX_CAPABLE_ACCESS XLNX_RO
#define ABILITY_REG_HALF_DUPLEX_CAPABLE_SHIFT 9
#define ABILITY_REG_HALF_DUPLEX_CAPABLE_DEFAULT 0x0
//Desc
#define ABILITY_REG_FRAME_FILTER_AVAILABLE_MASK 0x00000400
#define ABILITY_REG_FRAME_FILTER_AVAILABLE_ACCESS XLNX_RO
#define ABILITY_REG_FRAME_FILTER_AVAILABLE_SHIFT 10
#define ABILITY_REG_FRAME_FILTER_AVAILABLE_DEFAULT 0x0
//Desc
#define ABILITY_REG_PFC_SUPPORT_MASK 0x00010000
#define ABILITY_REG_PFC_SUPPORT_ACCESS XLNX_RO
#define ABILITY_REG_PFC_SUPPORT_SHIFT 16
#define ABILITY_REG_PFC_SUPPORT_DEFAULT 0x0

#define MDIO_SETUP_WORD_REG_OFFSET 0x00000500
//Desc
#define MDIO_SETUP_WORD_REG_CLOCK_DIVIDE_MASK 0x0000003F
#define MDIO_SETUP_WORD_REG_CLOCK_DIVIDE_ACCESS XLNX_RW
#define MDIO_SETUP_WORD_REG_CLOCK_DIVIDE_SHIFT 0
#define MDIO_SETUP_WORD_REG_CLOCK_DIVIDE_DEFAULT 0x0
//Desc
#define MDIO_SETUP_WORD_REG_MDIO_ENABLE_MASK 0x00000040
#define MDIO_SETUP_WORD_REG_MDIO_ENABLE_ACCESS XLNX_RW
#define MDIO_SETUP_WORD_REG_MDIO_ENABLE_SHIFT 6
#define MDIO_SETUP_WORD_REG_MDIO_ENABLE_DEFAULT 0x0

#define MDIO_CONTROL_WORD_REG_OFFSET 0x00000504
//Desc
#define MDIO_CONTROL_WORD_REG_MDIO_READY_MASK 0x00000080
#define MDIO_CONTROL_WORD_REG_MDIO_READY_ACCESS XLNX_RO
#define MDIO_CONTROL_WORD_REG_MDIO_READY_SHIFT 7
#define MDIO_CONTROL_WORD_REG_MDIO_READY_DEFAULT 0x0
//Desc
#define MDIO_CONTROL_WORD_REG_INITIATE_MASK 0x00000400
#define MDIO_CONTROL_WORD_REG_INITIATE_ACCESS XLNX_WO
#define MDIO_CONTROL_WORD_REG_INITIATE_SHIFT 11
#define MDIO_CONTROL_WORD_REG_INITIATE_DEFAULT 0x0
//Desc
#define MDIO_CONTROL_WORD_REG_TX_OP_MASK 0x0000C000
#define MDIO_CONTROL_WORD_REG_TX_OP_ACCESS XLNX_RW
#define MDIO_CONTROL_WORD_REG_TX_OP_SHIFT 14
#define MDIO_CONTROL_WORD_REG_TX_OP_DEFAULT 0x0
//Desc
#define MDIO_CONTROL_WORD_REG_TX_REGAD_MASK 0x001F0000
#define MDIO_CONTROL_WORD_REG_TX_REGAD_ACCESS XLNX_RW
#define MDIO_CONTROL_WORD_REG_TX_REGAD_SHIFT 16
#define MDIO_CONTROL_WORD_REG_TX_REGAD_DEFAULT 0x0
//Desc
#define MDIO_CONTROL_WORD_REG_TX_PHYAD_MASK 0x1F000000
#define MDIO_CONTROL_WORD_REG_TX_PHYAD_ACCESS XLNX_RW
#define MDIO_CONTROL_WORD_REG_TX_PHYAD_SHIFT 24
#define MDIO_CONTROL_WORD_REG_TX_PHYAD_DEFAULT 0x0

#define MDIO_WRITE_DATA_REG_OFFSET 0x00000508
//Desc
#define MDIO_WRITE_DATA_REG_WRITE_DATA_MASK 0x0000FFFF
#define MDIO_WRITE_DATA_REG_WRITE_DATA_ACCESS XLNX_RW
#define MDIO_WRITE_DATA_REG_WRITE_DATA_SHIFT 0
#define MDIO_WRITE_DATA_REG_WRITE_DATA_DEFAULT 0x0

#define MDIO_READ_DATA_REG_OFFSET 0x0000050C
//Desc
#define MDIO_READ_DATA_REG_READ_DATA_MASK 0x0000FFFF
#define MDIO_READ_DATA_REG_READ_DATA_ACCESS XLNX_RO
#define MDIO_READ_DATA_REG_READ_DATA_SHIFT 0
#define MDIO_READ_DATA_REG_READ_DATA_DEFAULT 0x0
//Desc
#define MDIO_READ_DATA_REG_MDIO_READY_MASK 0x00010000
#define MDIO_READ_DATA_REG_MDIO_READY_ACCESS XLNX_RO
#define MDIO_READ_DATA_REG_MDIO_READY_SHIFT 16
#define MDIO_READ_DATA_REG_MDIO_READY_DEFAULT 0x0

#define INTR_STATUS_REG_OFFSET 0x00000600
//Desc
#define INTR_STATUS_REG_MDIO_MASK 0x00000001
#define INTR_STATUS_REG_MDIO_ACCESS XLNX_RO
#define INTR_STATUS_REG_MDIO_SHIFT 0
#define INTR_STATUS_REG_MDIO_DEFAULT 0x0
//Desc
#define INTR_STATUS_REG_PTP_TX_MASK 0x00000002
#define INTR_STATUS_REG_PTP_TX_ACCESS XLNX_RO
#define INTR_STATUS_REG_PTP_TX_SHIFT 1
#define INTR_STATUS_REG_PTP_TX_DEFAULT 0x0
//Desc
#define INTR_STATUS_REG_PTP_RX_MASK 0x00000004
#define INTR_STATUS_REG_PTP_RX_ACCESS XLNX_RO
#define INTR_STATUS_REG_PTP_RX_SHIFT 2
#define INTR_STATUS_REG_PTP_RX_DEFAULT 0x0
//Desc
#define INTR_STATUS_REG_PTP_TIMER_MASK 0x00000008
#define INTR_STATUS_REG_PTP_TIMER_ACCESS XLNX_RO
#define INTR_STATUS_REG_PTP_TIMER_SHIFT 3
#define INTR_STATUS_REG_PTP_TIMER_DEFAULT 0x0


#define INTR_PENDING_REG_OFFSET 0x00000610
//Desc
#define INTR_PENDING_REG_MDIO_MASK 0x00000001
#define INTR_PENDING_REG_MDIO_ACCESS XLNX_RO
#define INTR_PENDING_REG_MDIO_SHIFT 0
#define INTR_PENDING_REG_MDIO_DEFAULT 0x0
//Desc
#define INTR_PENDING_REG_PTP_TX_MASK 0x00000002
#define INTR_PENDING_REG_PTP_TX_ACCESS XLNX_RO
#define INTR_PENDING_REG_PTP_TX_SHIFT 1
#define INTR_PENDING_REG_PTP_TX_DEFAULT 0x0
//Desc
#define INTR_PENDING_REG_PTP_RX_MASK 0x00000004
#define INTR_PENDING_REG_PTP_RX_ACCESS XLNX_RO
#define INTR_PENDING_REG_PTP_RX_SHIFT 2
#define INTR_PENDING_REG_PTP_RX_DEFAULT 0x0
//Desc
#define INTR_PENDING_REG_PTP_TIMER_MASK 0x00000008
#define INTR_PENDING_REG_PTP_TIMER_ACCESS XLNX_RO
#define INTR_PENDING_REG_PTP_TIMER_SHIFT 3
#define INTR_PENDING_REG_PTP_TIMER_DEFAULT 0x0

#define INTR_ENABLE_REG_OFFSET 0x00000620
//Desc
#define INTR_ENABLE_REG_MDIO_MASK 0x00000001
#define INTR_ENABLE_REG_MDIO_ACCESS XLNX_RW
#define INTR_ENABLE_REG_MDIO_SHIFT 0
#define INTR_ENABLE_REG_MDIO_DEFAULT 0x0
//Desc
#define INTR_ENABLE_REG_PTP_TX_MASK 0x00000002
#define INTR_ENABLE_REG_PTP_TX_ACCESS XLNX_RW
#define INTR_ENABLE_REG_PTP_TX_SHIFT 1
#define INTR_ENABLE_REG_PTP_TX_DEFAULT 0x0
//Desc
#define INTR_ENABLE_REG_PTP_RX_MASK 0x00000004
#define INTR_ENABLE_REG_PTP_RX_ACCESS XLNX_RW
#define INTR_ENABLE_REG_PTP_RX_SHIFT 2
#define INTR_ENABLE_REG_PTP_RX_DEFAULT 0x0
//Desc
#define INTR_ENABLE_REG_PTP_TIMER_MASK 0x00000008
#define INTR_ENABLE_REG_PTP_TIMER_ACCESS XLNX_RW
#define INTR_ENABLE_REG_PTP_TIMER_SHIFT 3
#define INTR_ENABLE_REG_PTP_TIMER_DEFAULT 0x0

#define INTR_CLEAR_REG_OFFSET 0x00000630
//Desc
#define INTR_CLEAR_REG_MDIO_MASK 0x00000001
#define INTR_CLEAR_REG_MDIO_ACCESS XLNX_WO
#define INTR_CLEAR_REG_MDIO_SHIFT 0
#define INTR_CLEAR_REG_MDIO_DEFAULT 0x0
//Desc
#define INTR_CLEAR_REG_PTP_TX_MASK 0x00000002
#define INTR_CLEAR_REG_PTP_TX_ACCESS XLNX_WO
#define INTR_CLEAR_REG_PTP_TX_SHIFT 1
#define INTR_CLEAR_REG_PTP_TX_DEFAULT 0x0
//Desc
#define INTR_CLEAR_REG_PTP_RX_MASK 0x00000004
#define INTR_CLEAR_REG_PTP_RX_ACCESS XLNX_WO
#define INTR_CLEAR_REG_PTP_RX_SHIFT 2
#define INTR_CLEAR_REG_PTP_RX_DEFAULT 0x0
//Desc
#define INTR_CLEAR_REG_PTP_TIMER_MASK 0x00000008
#define INTR_CLEAR_REG_PTP_TIMER_ACCESS XLNX_WO
#define INTR_CLEAR_REG_PTP_TIMER_SHIFT 3
#define INTR_CLEAR_REG_PTP_TIMER_DEFAULT 0x0

#define UNICAST_ADDRESS_WORD_0_REG_OFFSET 0x00000700
//Desc
#define UNICAST_ADDRESS_WORD_0_REG_UNICAST_ADDRESS_MASK 0xFFFFFFFF
#define UNICAST_ADDRESS_WORD_0_REG_UNICAST_ADDRESS_ACCESS XLNX_RW
#define UNICAST_ADDRESS_WORD_0_REG_UNICAST_ADDRESS_SHIFT 0
#define UNICAST_ADDRESS_WORD_0_REG_UNICAST_ADDRESS_DEFAULT 0xFFFFFFFF

#define UNICAST_ADDRESS_WORD_1_REG_OFFSET 0x00000704
//Desc
#define UNICAST_ADDRESS_WORD_1_REG_UNICAST_ADDRESS_MASK 0x0000FFFF
#define UNICAST_ADDRESS_WORD_1_REG_UNICAST_ADDRESS_ACCESS XLNX_RW
#define UNICAST_ADDRESS_WORD_1_REG_UNICAST_ADDRESS_SHIFT 0
#define UNICAST_ADDRESS_WORD_1_REG_UNICAST_ADDRESS_DEFAULT 0x0000FFFF

#define FRAME_FILTER_CONTROL_REG_OFFSET 0x00000708
//Desc
#define FRAME_FILTER_CONTROL_REG_FILTER_INDEX_MASK 0x0000000F
#define FRAME_FILTER_CONTROL_REG_FILTER_INDEX_ACCESS XLNX_RW
#define FRAME_FILTER_CONTROL_REG_FILTER_INDEX_SHIFT 0
#define FRAME_FILTER_CONTROL_REG_FILTER_INDEX_DEFAULT 0x00000000
//Desc
#define FRAME_FILTER_CONTROL_REG_AVB_SELECT_MASK 0x00000100
#define FRAME_FILTER_CONTROL_REG_AVB_SELECT_ACCESS XLNX_RW
#define FRAME_FILTER_CONTROL_REG_AVB_SELECT_SHIFT 0
#define FRAME_FILTER_CONTROL_REG_AVB_SELECT_DEFAULT 0x0
//Desc
#define FRAME_FILTER_CONTROL_REG_PROMISCUOUS_MODE_MASK 0x80000000
#define FRAME_FILTER_CONTROL_REG_PROMISCUOUS_MODE_ACCESS XLNX_RW
#define FRAME_FILTER_CONTROL_REG_PROMISCUOUS_MODE_SHIFT 32
#define FRAME_FILTER_CONTROL_REG_PROMISCUOUS_MODE_DEFAULT 0x1

#define FRAME_FILTER_ENABLE_REG_OFFSET 0x0000070C
//Desc
#define FRAME_FILTER_ENABLE_REG_FILTER_ENABLE_MASK 0x00000001
#define FRAME_FILTER_ENABLE_REG_FILTER_ENABLE_ACCESS XLNX_RW
#define FRAME_FILTER_ENABLE_REG_FILTER_ENABLE_SHIFT 0
#define FRAME_FILTER_ENABLE_REG_FILTER_ENABLE_DEFAULT 0x1

#define FRAME_FILTER_VALUE_BYTES_3_0_REG_OFFSET 0x00000710
//Desc
#define FRAME_FILTER_VALUE_BYTES_3_0_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_3_0_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_3_0_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_3_0_REG_FILTER_VALUE_DEFAULT 0xFFFFFFFF

#define FRAME_FILTER_VALUE_BYTES_7_4_REG_OFFSET 0x00000714
//Desc
#define FRAME_FILTER_VALUE_BYTES_7_4_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_7_4_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_7_4_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_7_4_REG_FILTER_VALUE_DEFAULT 0x0000FFFF

#define FRAME_FILTER_VALUE_BYTES_11_8_REG_OFFSET 0x00000718
//Desc
#define FRAME_FILTER_VALUE_BYTES_11_8_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_11_8_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_11_8_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_11_8_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_15_12_REG_OFFSET 0x0000071C
//Desc
#define FRAME_FILTER_VALUE_BYTES_15_12_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_15_12_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_15_12_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_15_12_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_19_16_REG_OFFSET 0x00000720
//Desc
#define FRAME_FILTER_VALUE_BYTES_19_16_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_19_16_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_19_16_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_19_16_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_23_20_REG_OFFSET 0x00000724
//Desc
#define FRAME_FILTER_VALUE_BYTES_23_20_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_23_20_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_23_20_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_23_20_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_27_24_REG_OFFSET 0x00000728
//Desc
#define FRAME_FILTER_VALUE_BYTES_27_24_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_27_24_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_27_24_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_27_24_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_31_28_REG_OFFSET 0x0000072C
//Desc
#define FRAME_FILTER_VALUE_BYTES_31_28_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_31_28_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_31_28_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_31_28_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_35_32_REG_OFFSET 0x00000730
//Desc
#define FRAME_FILTER_VALUE_BYTES_35_32_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_35_32_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_35_32_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_35_32_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_39_36_REG_OFFSET 0x00000734
//Desc
#define FRAME_FILTER_VALUE_BYTES_39_36_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_39_36_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_39_36_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_39_36_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_43_40_REG_OFFSET 0x00000738
//Desc
#define FRAME_FILTER_VALUE_BYTES_43_40_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_43_40_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_43_40_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_43_40_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_47_44_REG_OFFSET 0x0000073C
//Desc
#define FRAME_FILTER_VALUE_BYTES_47_44_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_47_44_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_47_44_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_47_44_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_51_48_REG_OFFSET 0x00000740
//Desc
#define FRAME_FILTER_VALUE_BYTES_51_48_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_51_48_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_51_48_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_51_48_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_55_52_REG_OFFSET 0x00000744
//Desc
#define FRAME_FILTER_VALUE_BYTES_55_52_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_55_52_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_55_52_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_55_52_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_59_56_REG_OFFSET 0x00000748
//Desc
#define FRAME_FILTER_VALUE_BYTES_59_56_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_59_56_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_59_56_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_59_56_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_VALUE_BYTES_63_60_REG_OFFSET 0x0000074C
//Desc
#define FRAME_FILTER_VALUE_BYTES_63_60_REG_FILTER_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_VALUE_BYTES_63_60_REG_FILTER_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_VALUE_BYTES_63_60_REG_FILTER_VALUE_SHIFT 0
#define FRAME_FILTER_VALUE_BYTES_63_60_REG_FILTER_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_3_0_REG_OFFSET 0x00000750
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_3_0_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_3_0_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_3_0_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_3_0_REG_FILTER_MASK_VALUE_DEFAULT 0xFFFFFFFF

#define FRAME_FILTER_MASK_VALUE_BYTES_7_4_REG_OFFSET 0x00000754
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_7_4_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_7_4_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_7_4_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_7_4_REG_FILTER_MASK_VALUE_DEFAULT 0x0000FFFF

#define FRAME_FILTER_MASK_VALUE_BYTES_11_8_REG_OFFSET 0x00000758
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_11_8_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_11_8_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_11_8_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_11_8_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_15_12_REG_OFFSET 0x0000075C
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_15_12_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_15_12_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_15_12_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_15_12_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_19_16_REG_OFFSET 0x00000760
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_19_16_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_19_16_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_19_16_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_19_16_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_23_20_REG_OFFSET 0x00000764
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_23_20_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_23_20_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_23_20_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_23_20_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_27_24_REG_OFFSET 0x00000768
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_27_24_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_27_24_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_27_24_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_27_24_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_31_28_REG_OFFSET 0x0000076C
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_31_28_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_31_28_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_31_28_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_31_28_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_35_32_REG_OFFSET 0x00000770
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_35_32_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_35_32_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_35_32_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_35_32_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_39_36_REG_OFFSET 0x00000774
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_39_36_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_39_36_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_39_36_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_39_36_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_43_40_REG_OFFSET 0x00000778
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_43_40_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_43_40_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_43_40_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_43_40_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_47_44_REG_OFFSET 0x0000077C
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_47_44_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_47_44_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_47_44_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_47_44_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_51_48_REG_OFFSET 0x00000780
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_51_48_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_51_48_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_51_48_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_51_48_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_55_52_REG_OFFSET 0x00000784
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_55_52_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_55_52_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_55_52_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_55_52_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_59_56_REG_OFFSET 0x00000788
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_59_56_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_59_56_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_59_56_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_59_56_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define FRAME_FILTER_MASK_VALUE_BYTES_63_60_REG_OFFSET 0x0000078C
//Desc
#define FRAME_FILTER_MASK_VALUE_BYTES_63_60_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define FRAME_FILTER_MASK_VALUE_BYTES_63_60_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define FRAME_FILTER_MASK_VALUE_BYTES_63_60_REG_FILTER_MASK_VALUE_SHIFT 0
#define FRAME_FILTER_MASK_VALUE_BYTES_63_60_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define PTP_FRAME_FILTER_VALUE_0_REG_OFFSET 0x00000710
//Desc
#define PTP_FRAME_FILTER_VALUE_0_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define PTP_FRAME_FILTER_VALUE_0_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define PTP_FRAME_FILTER_VALUE_0_REG_FILTER_MASK_VALUE_SHIFT 0
#define PTP_FRAME_FILTER_VALUE_0_REG_FILTER_MASK_VALUE_DEFAULT 0x00C28001

#define PTP_FRAME_FILTER_VALUE_1_REG_OFFSET 0x00000714
//Desc
#define PTP_FRAME_FILTER_VALUE_1_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define PTP_FRAME_FILTER_VALUE_1_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define PTP_FRAME_FILTER_VALUE_1_REG_FILTER_MASK_VALUE_SHIFT 0
#define PTP_FRAME_FILTER_VALUE_1_REG_FILTER_MASK_VALUE_DEFAULT 0x00000E00

#define PTP_FRAME_FILTER_VALUE_2_REG_OFFSET 0x00000718
//Desc
#define PTP_FRAME_FILTER_VALUE_2_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define PTP_FRAME_FILTER_VALUE_2_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define PTP_FRAME_FILTER_VALUE_2_REG_FILTER_MASK_VALUE_SHIFT 0
#define PTP_FRAME_FILTER_VALUE_2_REG_FILTER_MASK_VALUE_DEFAULT 0x00000000

#define PTP_FRAME_FILTER_VALUE_3_REG_OFFSET 0x0000071C
//Desc
#define PTP_FRAME_FILTER_VALUE_3_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define PTP_FRAME_FILTER_VALUE_3_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define PTP_FRAME_FILTER_VALUE_3_REG_FILTER_MASK_VALUE_SHIFT 0
#define PTP_FRAME_FILTER_VALUE_3_REG_FILTER_MASK_VALUE_DEFAULT 0x0000F788

#define PTP_FRAME_FILTER_MASK_VALUE_0_REG_OFFSET 0x00000750
//Desc
#define PTP_FRAME_FILTER_MASK_VALUE_0_REG_FILTER_MASK_MASK_VALUE_MASK 0xFFFFFFFF
#define PTP_FRAME_FILTER_MASK_VALUE_0_REG_FILTER_MASK_MASK_VALUE_ACCESS XLNX_RW
#define PTP_FRAME_FILTER_MASK_VALUE_0_REG_FILTER_MASK_MASK_VALUE_SHIFT 0
#define PTP_FRAME_FILTER_MASK_VALUE_0_REG_FILTER_MASK_MASK_VALUE_DEFAULT 0xFFFFFFFF

#define PTP_FRAME_FILTER_MASK_VALUE_1_REG_OFFSET 0x00000754
//Desc
#define PTP_FRAME_FILTER_MASK_VALUE_1_REG_FILTER_MASK_MASK_VALUE_MASK 0xFFFFFFFF
#define PTP_FRAME_FILTER_MASK_VALUE_1_REG_FILTER_MASK_MASK_VALUE_ACCESS XLNX_RW
#define PTP_FRAME_FILTER_MASK_VALUE_1_REG_FILTER_MASK_MASK_VALUE_SHIFT 0
#define PTP_FRAME_FILTER_MASK_VALUE_1_REG_FILTER_MASK_MASK_VALUE_DEFAULT 0x0000FFFF

#define PTP_FRAME_FILTER_MASK_VALUE_2_REG_OFFSET 0x00000758
//Desc
#define PTP_FRAME_FILTER_MASK_VALUE_2_REG_FILTER_MASK_MASK_VALUE_MASK 0xFFFFFFFF
#define PTP_FRAME_FILTER_MASK_VALUE_2_REG_FILTER_MASK_MASK_VALUE_ACCESS XLNX_RW
#define PTP_FRAME_FILTER_MASK_VALUE_2_REG_FILTER_MASK_MASK_VALUE_SHIFT 0
#define PTP_FRAME_FILTER_MASK_VALUE_2_REG_FILTER_MASK_MASK_VALUE_DEFAULT 0x00000000

#define PTP_FRAME_FILTER_MASK_VALUE_3_REG_OFFSET 0x0000075C
//Desc
#define PTP_FRAME_FILTER_MASK_VALUE_3_REG_FILTER_MASK_MASK_VALUE_MASK 0xFFFFFFFF
#define PTP_FRAME_FILTER_MASK_VALUE_3_REG_FILTER_MASK_MASK_VALUE_ACCESS XLNX_RW
#define PTP_FRAME_FILTER_MASK_VALUE_3_REG_FILTER_MASK_MASK_VALUE_SHIFT 0
#define PTP_FRAME_FILTER_MASK_VALUE_3_REG_FILTER_MASK_MASK_VALUE_DEFAULT 0x0000FFFF

#define SR_CLASS_A_FRAME_FILTER_VALUE_REG_OFFSET 0x0000071C
//Desc
#define SR_CLASS_A_FRAME_FILTER_VALUE_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define SR_CLASS_A_FRAME_FILTER_VALUE_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define SR_CLASS_A_FRAME_FILTER_VALUE_REG_FILTER_MASK_VALUE_SHIFT 0
#define SR_CLASS_A_FRAME_FILTER_VALUE_REG_FILTER_MASK_VALUE_DEFAULT 0x02600081

#define SR_CLASS_A_FRAME_FILTER_MASK_VALUE_REG_OFFSET 0x0000075C
//Desc
#define SR_CLASS_A_FRAME_FILTER_MASK_VALUE_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define SR_CLASS_A_FRAME_FILTER_MASK_VALUE_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define SR_CLASS_A_FRAME_FILTER_MASK_VALUE_REG_FILTER_MASK_VALUE_SHIFT 0
#define SR_CLASS_A_FRAME_FILTER_MASK_VALUE_REG_FILTER_MASK_VALUE_DEFAULT 0xFFFFFFFF

#define SR_CLASS_B_FRAME_FILTER_VALUE_REG_OFFSET 0x0000071C
//Desc
#define SR_CLASS_B_FRAME_FILTER_VALUE_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define SR_CLASS_B_FRAME_FILTER_VALUE_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define SR_CLASS_B_FRAME_FILTER_VALUE_REG_FILTER_MASK_VALUE_SHIFT 0
#define SR_CLASS_B_FRAME_FILTER_VALUE_REG_FILTER_MASK_VALUE_DEFAULT 0x02600081

#define SR_CLASS_B_FRAME_FILTER_MASK_VALUE_REG_OFFSET 0x0000075C
//Desc
#define SR_CLASS_B_FRAME_FILTER_MASK_VALUE_REG_FILTER_MASK_VALUE_MASK 0xFFFFFFFF
#define SR_CLASS_B_FRAME_FILTER_MASK_VALUE_REG_FILTER_MASK_VALUE_ACCESS XLNX_RW
#define SR_CLASS_B_FRAME_FILTER_MASK_VALUE_REG_FILTER_MASK_VALUE_SHIFT 0
#define SR_CLASS_B_FRAME_FILTER_MASK_VALUE_REG_FILTER_MASK_VALUE_DEFAULT 0xFFFFFFFF

#define TX_PTP_PKT_BUFFER_CTRL_REG_OFFSET 0x00012000
//Desc
#define TX_PTP_PKT_BUFFER_CTRL_REG_TX_SEND_FRAME_BITS_MASK 0x000000FF
#define TX_PTP_PKT_BUFFER_CTRL_REG_TX_SEND_FRAME_BITS_ACCESS XLNX_WO
#define TX_PTP_PKT_BUFFER_CTRL_REG_TX_SEND_FRAME_BITS_SHIFT 0
#define TX_PTP_PKT_BUFFER_CTRL_REG_TX_SEND_FRAME_BITS_DEFAULT 0x0
//Desc
#define TX_PTP_PKT_BUFFER_CTRL_REG_TX_FRAME_WAITING_INDICATION_MASK 0x0000FF00
#define TX_PTP_PKT_BUFFER_CTRL_REG_TX_FRAME_WAITING_INDICATION_ACCESS XLNX_RO
#define TX_PTP_PKT_BUFFER_CTRL_REG_TX_FRAME_WAITING_INDICATION_SHIFT 8
#define TX_PTP_PKT_BUFFER_CTRL_REG_TX_FRAME_WAITING_INDICATION_DEFAULT 0x0
//Desc
#define TX_PTP_PKT_BUFFER_CTRL_REG_TX_PACKET_MASK 0x00070000
#define TX_PTP_PKT_BUFFER_CTRL_REG_TX_PACKET_ACCESS XLNX_RO
#define TX_PTP_PKT_BUFFER_CTRL_REG_TX_PACKET_SHIFT 16
#define TX_PTP_PKT_BUFFER_CTRL_REG_TX_PACKET_DEFAULT 0x0

#define RX_PTP_PKT_BUFFER_CTRL_REG_OFFSET 0x00012004
//Desc
#define RX_PTP_PKT_BUFFER_CTRL_REG_RX_CLEAR_MASK 0x00000001
#define RX_PTP_PKT_BUFFER_CTRL_REG_RX_CLEAR_ACCESS XLNX_WO
#define RX_PTP_PKT_BUFFER_CTRL_REG_RX_CLEAR_SHIFT 0
#define RX_PTP_PKT_BUFFER_CTRL_REG_RX_CLEAR_DEFAULT 0x0
//Desc
#define RX_PTP_PKT_BUFFER_CTRL_REG_RX_PACKET_MASK 0x00000F00
#define RX_PTP_PKT_BUFFER_CTRL_REG_RX_PACKET_ACCESS XLNX_RO
#define RX_PTP_PKT_BUFFER_CTRL_REG_RX_PACKET_SHIFT 8
#define RX_PTP_PKT_BUFFER_CTRL_REG_RX_PACKET_DEFAULT 0x0

#define TX_ARBITER_SEND_SLOPE_CTL_REG_OFFSET 0x0001200C
//Desc
#define TX_ARBITER_SEND_SLOPE_CTL_REG_VAL_SEND_SLOPE_MASK 0x000FFFFF
#define TX_ARBITER_SEND_SLOPE_CTL_REG_VAL_SEND_SLOPE_ACCESS XLNX_RW
#define TX_ARBITER_SEND_SLOPE_CTL_REG_VAL_SEND_SLOPE_SHIFT 0
#define TX_ARBITER_SEND_SLOPE_CTL_REG_VAL_SEND_SLOPE_DEFAULT 0x800

#define TX_ARBITER_IDLE_SLOPE_CTL_REG_OFFSET 0x00012010
//Desc
#define TX_ARBITER_IDLE_SLOPE_CTL_REG_VAL_SEND_SLOPE_MASK 0x000FFFFF
#define TX_ARBITER_IDLE_SLOPE_CTL_REG_VAL_SEND_SLOPE_ACCESS XLNX_RW
#define TX_ARBITER_IDLE_SLOPE_CTL_REG_VAL_SEND_SLOPE_SHIFT 0
#define TX_ARBITER_IDLE_SLOPE_CTL_REG_VAL_SEND_SLOPE_DEFAULT 0x1800

#define RTC_NANOSEC_FIELD_OFFSET_REG_OFFSET 0x00012800
//Desc
#define RTC_NANOSEC_FIELD_OFFSET_REG_OFFSET_NANOSEC_MASK 0x3FFFFFFF
#define RTC_NANOSEC_FIELD_OFFSET_REG_OFFSET_NANOSEC_ACCESS XLNX_RW
#define RTC_NANOSEC_FIELD_OFFSET_REG_OFFSET_NANOSEC_SHIFT 0
#define RTC_NANOSEC_FIELD_OFFSET_REG_OFFSET_NANOSEC_DEFAULT 0x0

#define RTC_SEC_FIELD_OFFSET_BITS_31_0_REG_OFFSET 0x00012808
//Desc
#define RTC_SEC_FIELD_OFFSET_BITS_31_0_REG_OFFSET_SEC_MASK 0xFFFFFFFF
#define RTC_SEC_FIELD_OFFSET_BITS_31_0_REG_OFFSET_SEC_ACCESS XLNX_RW
#define RTC_SEC_FIELD_OFFSET_BITS_31_0_REG_OFFSET_SEC_SHIFT 0
#define RTC_SEC_FIELD_OFFSET_BITS_31_0_REG_OFFSET_SEC_DEFAULT 0x0

#define RTC_SEC_FIELD_OFFSET_BITS_47_32_REG_OFFSET 0x0001280C
//Desc
#define RTC_SEC_FIELD_OFFSET_BITS_47_32_REG_OFFSET_SEC_MASK 0x0000FFFF
#define RTC_SEC_FIELD_OFFSET_BITS_47_32_REG_OFFSET_SEC_ACCESS XLNX_RW
#define RTC_SEC_FIELD_OFFSET_BITS_47_32_REG_OFFSET_SEC_SHIFT 0
#define RTC_SEC_FIELD_OFFSET_BITS_47_32_REG_OFFSET_SEC_DEFAULT 0x0

#define RTC_INCREMENT_VAL_REG_OFFSET 0x00012810
//Desc
#define RTC_INCREMENT_VAL_REG_OFFSET_NANOSEC_MASK 0x03FFFFFF
#define RTC_INCREMENT_VAL_REG_OFFSET_NANOSEC_ACCESS XLNX_RW
#define RTC_INCREMENT_VAL_REG_OFFSET_NANOSEC_SHIFT 0
#define RTC_INCREMENT_VAL_REG_OFFSET_NANOSEC_DEFAULT 0x0

#define CURRENT_RTC_NANOSEC_FIELD_VAL_REG_OFFSET 0x00012814
//Desc
#define CURRENT_RTC_NANOSEC_FIELD_VAL_REG_VAL_RTC_NANOSEC_FIELD_MASK 0x3FFFFFFF
#define CURRENT_RTC_NANOSEC_FIELD_VAL_REG_VAL_RTC_NANOSEC_FIELD_ACCESS XLNX_RO
#define CURRENT_RTC_NANOSEC_FIELD_VAL_REG_VAL_RTC_NANOSEC_FIELD_SHIFT 0
#define CURRENT_RTC_NANOSEC_FIELD_VAL_REG_VAL_RTC_NANOSEC_FIELD_DEFAULT 0x0

#define CURRENT_RTC_SEC_FIELD_VAL_BITS_31_0_REG_OFFSET 0x00012818
//Desc
#define CURRENT_RTC_SEC_FIELD_VAL_BITS_31_0_REG_VAL_RTC_SEC_MASK 0xFFFFFFFF
#define CURRENT_RTC_SEC_FIELD_VAL_BITS_31_0_REG_VAL_RTC_SEC_ACCESS XLNX_RO
#define CURRENT_RTC_SEC_FIELD_VAL_BITS_31_0_REG_VAL_RTC_SEC_SHIFT 0
#define CURRENT_RTC_SEC_FIELD_VAL_BITS_31_0_REG_VAL_RTC_SEC_DEFAULT 0x0

#define CURRENT_RTC_SEC_FIELD_VAL_BITS_47_32_REG_OFFSET 0x0001281C
//Desc
#define CURRENT_RTC_SEC_FIELD_VAL_BITS_47_32_REG_VAL_RTC_SEC_MASK 0x0000FFFF
#define CURRENT_RTC_SEC_FIELD_VAL_BITS_47_32_REG_VAL_RTC_SEC_ACCESS XLNX_RO
#define CURRENT_RTC_SEC_FIELD_VAL_BITS_47_32_REG_VAL_RTC_SEC_SHIFT 0
#define CURRENT_RTC_SEC_FIELD_VAL_BITS_47_32_REG_VAL_RTC_SEC_DEFAULT 0x0

#define RTC_INTR_CLEAR_REG_OFFSET 0x00012820
//Desc
#define RTC_INTR_CLEAR_REG_CLEAR_MASK 0x00000001
#define RTC_INTR_CLEAR_REG_CLEAR_ACCESS XLNX_WO
#define RTC_INTR_CLEAR_REG_CLEAR_SHIFT 0
#define RTC_INTR_CLEAR_REG_CLEAR_DEFAULT 0x0

#define RTC_PHASE_ADJ_REG_OFFSET 0x00012824
//Desc
#define RTC_PHASE_ADJ_REG_VAL_RTC_NANOSEC_FIELD_MASK 0x3FFFFFFF
#define RTC_PHASE_ADJ_REG_VAL_RTC_NANOSEC_FIELD_ACCESS XLNX_RW
#define RTC_PHASE_ADJ_REG_VAL_RTC_NANOSEC_FIELD_SHIFT 0
#define RTC_PHASE_ADJ_REG_VAL_RTC_NANOSEC_FIELD_DEFAULT 0x0

